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I2C vs SPI Protocol Guide: Choosing the Right Bus for Your Design

I2C vs SPI Protocol Guide: Choosing the Right Bus for Your Design

Embedded Systems Embedded Systems 8 min read 1566 words Beginner ExcellentWiki Editorial Team

Serial Communication in Embedded Systems

I2C and SPI are the two most widely used serial communication protocols in embedded systems, together connecting microcontrollers to the vast majority of peripheral devices. Understanding their electrical characteristics, timing requirements, protocol overhead, and design trade-offs is essential for creating reliable embedded hardware. The I2C bus specification, maintained by NXP Semiconductors (originally Philips), defines the electrical and protocol standards for the Inter-Integrated Circuit bus. The SPI protocol, originally defined by Motorola, has no formal standards body but is implemented consistently across virtually all semiconductor manufacturers. Choosing the wrong protocol or implementing it incorrectly can cause intermittent communication failures that are extremely difficult to debug in production.

I2C Protocol

I2C (Inter-Integrated Circuit) uses a two-wire bus consisting of serial data (SDA) and serial clock (SCL). Communication is half-duplex with multi-master capability through bus arbitration. Each device on the bus has a unique 7-bit or 10-bit address, allowing up to 112 devices on the same bus (16 reserved addresses). Standard mode operates at 100 kHz, Fast mode at 400 kHz, Fast Mode Plus at 1 MHz, and High-Speed mode at 3.4 MHz. The open-drain output structure requires external pull-up resistors connected to the supply voltage, typically 4.7 kΩ for 100 kHz operation with a bus capacitance under 200 pF. Clock stretching provides flow control when a slave is not ready to transmit — the slave holds SCL LOW to pause the master until it is ready to continue.

Pros: Only two bus signals regardless of the number of devices, built-in device addressing eliminates chip-select lines, multi-master arbitration with bus conflict detection, and acknowledge bits after every byte provide immediate error detection. Cons: Slower than SPI because open-drain pull-up resistors limit rise time and thus maximum clock frequency, pull-up resistors consume power proportional to frequency and bus voltage, bus capacitance limits the maximum number of devices and practical speed, and the two-wire interface cannot operate at extremely low standby power.

i2c_start();
i2c_write(dev_addr << 1 | 0);
i2c_write(reg_addr);
i2c_write(data);
i2c_stop();

SPI Protocol

SPI (Serial Peripheral Interface) uses four dedicated wires: master-out-slave-in (MOSI) for data from the master to the slave, master-in-slave-out (MISO) for data from the slave to the master, serial clock (SCLK) generated by the master, and slave select (SS) that the master asserts LOW to select a specific slave device. Communication is full-duplex — data shifts out on MOSI simultaneously with data shifting in on MISO. The push-pull outputs drive HIGH and LOW actively, eliminating pull-up resistors and enabling much higher clock speeds. Multiple slaves require separate chip-select lines from the master (or a chip-select decoder), adding one pin per slave. Four SPI modes, defined by clock polarity (CPOL) and clock phase (CPHA), accommodate different slave device timing requirements.

Pros: Very high speed (tens to hundreds of MHz), full-duplex communication doubles throughput for data-intensive applications, simple hardware implementation with no addressing overhead or acknowledge bits, and lower power in idle state because push-pull outputs do not dissipate pull-up current. Cons: More I/O pins required (each slave adds a chip select), no built-in device addressing or discovery, no hardware acknowledgment (the master must verify data through application-level mechanisms), and no flow control — the master must know the slave’s timing limits.

cs_low();
spi_transfer(reg_addr);
spi_transfer(data);
cs_high();

When to Use Each Protocol

Use I2C when the system includes many peripheral devices but has limited available GPIO pins, when moderate data rates under 3.4 MHz are sufficient for the application, when multi-master bus operation is required for redundancy, or when peripheral devices are physically distant on the same board requiring fewer traces. Use SPI when high data throughput is needed for display updates, SD card access, or high-speed ADC sampling exceeding I2C’s limits, when full-duplex communication is required for real-time data streaming, when the system has sufficient GPIO pins for each slave’s chip select, or when protocol overhead must be minimized for efficiency.

Bus Design Considerations

I2C Pull-Up Resistor Selection

The pull-up resistor value directly affects signal integrity, maximum bus speed, and power consumption. Too high a resistance produces slow signal rise times that may violate the timing specification, especially at higher bus speeds. Too low a resistance draws excessive current through the open-drain output drivers when they pull LOW, potentially exceeding the maximum IOL specification of the slowest device on the bus. Rule of thumb: 4.7 kΩ for 100 kHz Standard mode, 2.2 kΩ for 400 kHz Fast mode, 1.0 kΩ for 1 MHz Fast Mode Plus. Total bus capacitance should not exceed 400 pF for reliable operation.

SPI Signal Integrity at High Speed

At SPI clock frequencies above 20 MHz, signal integrity becomes a significant challenge. PCB trace lengths between master and slave must be matched within 10% of each other to minimize clock-to-data skew. Stub lengths from the main trace to each slave should be under 5 mm. Series termination resistors (22–33 Ω) placed at the source reduce ringing caused by transmission line reflections. For communication over cables longer than 5 cm, reduce the clock speed to under 5 MHz or use differential signaling such as LVDS with an interface chipset.

Troubleshooting Protocol Issues

When a serial communication bus malfunctions, a systematic approach quickly identifies the root cause. First, verify power supply voltages at each device’s power pins with a multimeter — a common failure is insufficient voltage or current. Check all connection continuity. Use an oscilloscope to probe the clock line and verify the master generates the expected frequency with correct voltage levels. For I2C, verify SCL and SDA idle HIGH and that the start condition (SDA falling while SCL HIGH) is generated correctly. For SPI, verify the chip select line goes LOW for the expected duration and the clock polarity and phase match the slave device specification. A logic analyzer captures the full transaction and decodes it, immediately revealing addressing errors, missing acknowledge bits, and incorrect register addresses.

Protocol Selection Decision Guide

When starting a new design, follow this decision process for serial protocol selection. Count the number of peripheral devices and available GPIO pins on the MCU. If fewer than three pins are available for serial interfaces, I2C is the only choice for multi-device buses. If high throughput is required — display updates above 1 MB/s, continuous ADC streaming above 100 kSPS — SPI is necessary. If peripherals are physically distributed across the board and reducing trace count matters, I2C’s two-wire bus is advantageous. If the design includes a mix of high-speed and low-speed peripherals, consider using both protocols on separate buses: SPI for the display and SD card, I2C for the sensors and RTC.

Power Consumption Considerations

I2C’s open-drain outputs consume dynamic power proportional to bus frequency and pull-up resistor value. At 400 kHz with 2.2 kΩ pull-ups, the bus can draw several milliamps during active communication. SPI’s push-pull outputs draw current only during signal transitions and have essentially zero static power draw, making SPI more power-efficient for intermittent communication. For battery-powered designs, disable pull-up resistors or use GPIO-controlled FETs to disconnect I2C pull-ups when the bus is idle.

Noise Immunity and Cable Length

I2C’s open-drain signaling is susceptible to noise on long traces. Maximum practical cable length for I2C is about 1 meter at 100 kHz with properly sized pull-ups and twisted pairs. SPI with push-pull outputs can drive cables up to 3 meters at reduced clock speeds (under 5 MHz). For longer distances, use differential protocols like RS-485 or CAN, or add dedicated bus buffer chips. For I2C, the PCA9600 differential buffer extends reach to hundreds of meters.

Frequently Asked Questions

Can I use multiple identical I2C sensors on the same bus? Only if they have configurable address pins. Most sensors provide 1–3 address selection pins (often labeled AD0, AD1), supporting 2–8 unique addresses. For more devices, use an I2C multiplexer such as the TCA9548A which provides 8 selectable downstream channels.

What causes I2C bus hangs and how do I recover? A hung bus occurs when a slave holds SDA LOW indefinitely, usually due to a protocol error or incomplete transaction. Recovery requires toggling SCL for nine clock cycles while monitoring SDA — if SDA goes HIGH after nine cycles, issue a STOP condition. Some MCU I2C peripherals include hardware bus recovery.

What is the maximum SPI cable length? SPI is designed for on-PCB communication. For cables longer than 10 cm, reduce speed to under 5 MHz and use shielded cables. For longer distances, use RS-422 with differential signaling or switch to CAN or Ethernet.

How do I determine the correct SPI mode for a device? Check the device datasheet timing diagram. The diagram shows when data is driven and when it is sampled relative to the clock edge. Mode 0 (clock idles LOW, data sampled on rising edge) is the most common and should be tried first.

What is I2C clock stretching and should I support it? Clock stretching allows a slow slave to hold the clock LOW while it prepares data. All I2C masters should support clock stretching for maximum compatibility, although many modern sensors operate fast enough to avoid needing it.

Can I mix 3.3V and 5V devices on the same I2C bus? Yes, if you use a bus voltage compatible with all devices and ensure that all devices tolerate the bus voltage. Use a level shifter (e.g., PCA9306) when mixing 3.3V and 5V domains. Many modern sensors are 3.3V only and will be damaged by 5V bus voltage.

Related: Sensor Interfacing | Microcontrollers Basics

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